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description the SM5K3/5k4/5k5 are cmos 4-bit single-chip microcomputers incorporating 4-bit parallel pro- cessing function, rom, ram, 10-bit a/d converter and timer/counters. it provides three kinds of interrupts and 4 levels subroutine stack. being fabricated through cmos process, the chip requires less power and available in a small package : best suitable for low power controlling, compact equipment like a precision charger. features ?rom capacity : 2 048 x 8 bits ?ram capacity : 128 x 4 bits ?instruction sets : 50 ?subroutine nesting : 4 levels ?i/o port : input 8 output 4 input/output 12 (36qfp/32sop) 11 (30sdip) 8 (28sop) ?interrupts : internal interrupt x 1 (timer) external interrupt x 2 (2 external interrupt inputs) ?a/d converter : resolution 10 bits channels 4 ?timer/counter : 8-bit x 1 ?built-in main clock oscillator for system clock ceramic/crystal oscillator (SM5K3/5k5) cr oscillator (sm5k4) ? signal generation for real time clock * (SM5K3/5k5) ?built-in 15 stages divider ( for real time clock * : SM5K3/5k5) ?instruction cycle time : 1 s (min.) (2 mhz, at 5 v 10%) (SM5K3/5k5) 2 s (min.) (1 mhz, at 2.2 to 5.5 v) (SM5K3/5k5) 1 s (min.) (1.67 mhz 20%, at 5 v 10%) (sm5k4) ?large current output pins (led direct drive) : 15ma (typ.) x 4 (sink current) ? supply voltages : 2.2 to 5.5 v (SM5K3/5k5) 2.7 to 5.5 v (sm5k4) ? packages : 30-pin sdip (sdip030-p-0400) 32-pin sop (sop032-p-0525) 36-pin qfp (qfp036-p-1010) 28-pin sop (sop028-p-0450) (SM5K3/5k5) 24-pin ssop (ssop024-p-0275) (sm5k4) * in case of using crystal oscillator SM5K3/sm5k4/sm5k5 SM5K3/sm5k4 sm5k5 4-bit single-chip microcomputers (controllers with 10-bit a/d converter) - 1 - in the absence of confirmation by device specification sheets, sharp takes no responsibility for any defects that may occur in equipment using any sharp devices shown in catalogs, data books, etc. contact sharp in order to obtain the latest device specification sheets before using any sharp device.
- 2 - 1 2 3 4 5 6 7 8 9 p1 3 p1 2 p1 1 p1 0 (nc) p0 3 p0 2 p0 1 p0 0 osc out v dd reset vr (nc) p3 0 p3 1 p3 2 p3 3 p2 0 p2 1 p2 2 (nc) gnd p5 0 p5 1 p2 3 osc in p4 3 p4 2 p4 1 p5 3 gnd (nc) p5 2 p4 0 agnd 27 26 25 24 23 22 21 20 19 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 36-pin qfp 10 11 12 13 14 p4 1 p4 2 p4 3 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 gnd p4 0 agnd p3 3 p3 2 p3 1 p3 0 vr reset v dd osc out osc in p2 3 gnd 1 2 3 4 5 6 7 8 9 SM5K3/sm5k4/sm5k5 pin connections p5 3 p4 1 p4 2 p4 3 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 gnd p4 0 agnd p3 3 p3 2 p3 1 p3 0 vr reset v dd osc out osc in p2 3 p5 1 p5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10 11 12 13 14 15 16 p5 3 p4 1 p4 2 p4 3 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 gnd p5 2 p4 0 agnd p3 3 p3 2 p3 1 p3 0 vr reset v dd osc out osc in p2 3 p5 1 p5 0 1 2 3 4 5 6 7 8 9 30-pin sdip 32-pin sop top view 28-pin sop (SM5K3/5k5) 10 11 12 p4 1 p4 2 p4 3 p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p2 0 p2 1 p2 2 24 23 22 21 20 19 18 17 16 15 14 13 gnd p4 0 agnd p3 2 p3 1 p3 0 vr reset v dd osc out osc in p2 3 1 2 3 4 5 6 7 8 9 24-pin ssop (sm5k4)
- 3 - SM5K3/sm5k4/sm5k5 block diagram nomenclature a : a register a/d : a/d converter unit alu : arithmetic logic unit b m , b l : ram address register c : carry flag ifa, ifb, ift : interrupt request flag ime : interrupt master enable flag inst. dec. : instruction decoder int : interrupt control unit p0-p5 : port register p u , p l : program counter r8, r9, rc, re, rf : mode register ra : count register rb : modulo register sb : sb register sr : stack register p0 0 p0 1 p0 2 p0 3 p1 0 p1 1 p1 2 p1 3 p2 0 p2 1 p2 2 p2 3 p3 0 p3 1 p3 2 p3 3 p4 0 p4 1 p4 2 p4 3 p5 0 p5 1 p5 2 p5 3 p2 p0 p1 p3 p4 p5 ift ifa ifb fr r3 int a/d vr agnd osc rc rb re sr x 4 prescaler sr (8) p u (5) p l (6) b m (4) b l (4) ime ra interrupt controller dec dec x (4) a (4) c alu rom v dd gnd osc in osc out reset 2 048-byte 128 x 4-bit ram r8 r9 inst.dec. selector alu
- 4 - parameter SM5K3/sm5k4/sm5k5 pin description absolute maximum ratings symbol i/o function p0 0 -p0 3 o high current output (sink current 15 ma) p1 0 -p1 1 i input (standby release) (counter input : p1 1 ) with pull-up resistor p1 2 -p1 3 i input (standby release) with pull-up resistor p2 0 -p2 3 i/o input (with pull-up resistor) or output (independent) p3 0 -p3 3 i input (also used as analog input) with pull-up resistor p4 0 -p4 3 , p5 0 -p5 3 i/o input (with pull-up resistor) and output osc in , osc out i/o ceramic/crystal oscillation pin (SM5K3/5k5)/cr oscillation pin (sm5k4) reset i reset signal input with pull-up resistor vr, agnd i a/d converter reference supply input port v dd , gnd i power supply, ground symbol conditions rating unit supply voltage v dd 0.3 to +7.0 v input voltage v i 0.3 to v dd +0.3 v output voltage v o 0.3 to v dd +0.3 v maximum output current i oh high-level output current (all outputs) 4 ma i ol0 low-level output current ( p0 0 -p0 3 ) 30 ma i ol1 low-level output current (all but p0 0 -p0 3 ) 4 ma total output current ioh high-level output current (all outputs) 20 ma iol low-level output current (all outputs) 80 ma t opr ?0 to +70 (SM5K3/5k5) ?0 to +85 (sm5k4) ? storage temperature t stg ?5 to +150 ? operating temperature note : symbols apply to 32-pin sop and 36-pin qfp. ( in case of 30-pin sdip, p5 2 does not exist. in case of 28-pin sop, p5 0 -p5 3 do not exist. in case of 24-pin ssop, p1 2, p1 3, p3 3, p5 0- p5 3 pins do not exist.)
- 5 - SM5K3/sm5k4/sm5k5 recommended operating conditions (SM5K3/5k5) parameter symbol conditions rating unit supply voltage v dd 2.2 to 5.5 v instruction cycle t sys v dd = 2.2 to 5.5 v 2 to 61 ? v dd = 5.0 v 10% 1 to 61 main clock frequency (osc in -osc out ) f osc v dd = 2.2 to 5.5 v 1 m to 32.768 k hz v dd = 5.0 v 10% 2 m to 32.768 k (sm5k4) notes : the typical oscillation frequency shall be determined in consideration of operating condition and fluctuation frequency. mount rf, rd, c 1 , c 2 , oscillator (SM5K3/5k5)/rf (sm5k4) as close as possible to the oscillator pins of the lsi, in order to reduce an influence from floating capacitance. since the value of resistor rf, rd, c 1 , c 2 , oscillator (SM5K3/5k5)/rf (sm5k4) varies depending on circuit pattern and others, the final rf, rd, c 1 , c 2 , oscillator (SM5K3/5k5)/rf (sm5k4) value shall be determined on the actual unit. don't connect any line to osc in and osc out except oscillator circuit. ?don't put any signal line across the oscillator circuit line. on the multilayer circuit, do not let the oscillator circuit wiring cross other circuit. ?minimize the wiring capacitance of gnd and v dd . oscillation circuit parameter symbol conditions rating unit supply voltage v dd 2.7 to 5.5 v instruction cycle t sys v dd = 2.7 to 5.5 v 2 to 5 ? v dd = 5.0 v 10% 1 to 5 main clock frequency * (osc in -osc out ) f osc v dd = 2.7 to 5.5 v 1 m to 400 k hz v dd = 5.0 v 10% 2 m to 400 k * degree of fluctuation frequency : 20% osc out osc in rf rf = 33 k w (fosc = 1.67 mhz, typ.) ?SM5K3/5k5 * reference only : circuit configuration varies according to oscillator used. ?sm5k4 osc out osc in rf rd oscillator c 1 c 2
- 6 - notes : 1. applicable pins : p1 2 , p1 3 , p2 0 -p2 3 , p3 0 -p3 3 (digital input mode), p4 0 -p4 3 p5 0 -p5 3 2. applicable pins : osc in , reset, p1 0 , p1 1 3. applicable pins : r eset, p1 0 -p1 3 , p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (digital input mode) 4. applicable pins : p3 0 -p3 3 (analog input mode) 5. applicable pins : p0 0 -p0 3 (high current mode) 6. applicable pins : p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (output mode) * 1 7. applicable pins : p3 0 -p3 3 * 2 8. no load (a/d conversion is stop.) 9. a/d conversion in operation (operation enable) 10. a/d conversion in stop (operation disable) * 1 in case of 32-pin sop and 36-pin qfp. (in case of 30-pin sdip, p5 2 dose not exist. in case of 28-pin sop, p5 0 -p5 3 do not exist.) * 2 p3 ports are normally used for input ports with pull-up resistor. these ports can be also used. SM5K3/sm5k4/sm5k5 v ih1 0.8 x v dd v dd v1 v il1 0 0.2 x v dd v ih2 0.9 x v dd v dd v2 v il2 0 0.1 x v dd v dd = 2.2 to 3.3 v 2 25 90 i il1 v in = 0 v v dd = 4.5 to 5.5 v 25 70 250 a 3 i ih1 v in = v dd 2 i il2 v in = 0 v 1.0 10 ? 4 i ih2 v in = v dd 1.0 10 v dd = 2.2 to 3.3 v 5 15 i ol1 v o = 1.0 v v dd = 4.5 to 5.5 v 15 25 ma 5 v dd = 2.2 to 3.3 v 0.3 1.5 i oh1 v o = v dd ?0.5 v v dd = 4.5 to 5.5 v 1.0 2.2 v dd = 2.2 to 3.3 v 1.2 5.0 i ol2 v o = 1.5 v v dd = 4.5 to 5.5 v 5 9.0 ma 6 v dd = 2.2 to 3.3 v 0.3 2.0 i oh2 v o = v dd ?0.5 v v dd = 4.5 to 5.5 v 1.0 2.4 v dd = 2.2 to 3.3 v 0.15 i oh3 v oh = v dd ?1.0 v ma 7 v dd = 4.5 to 5.5 v 0.5 f osc = 2 mhz v dd = 4.5 to 5.5 v 1 200 2 500 v dd = 2.2 to 3.3 v 300 800 f osc = 1 mhz i dd v dd = 4.5 to 5.5 v 600 1 200 f osc = 32.768 khz v dd = 2.2 to 3.3 v 20 120 (crystal osc mode) f osc = 2 mhz v dd = 4.5 to 5.5 v 760 1 500 v dd = 2.2 to 3.3 v 200 600 a 8 f osc = 1 mhz i hlt v dd = 4.5 to 5.5 v 400 900 f osc = 32.768 khz v dd = 2.2 to 3.3 v 20 75 (crystal osc mode) ceramic osc mode v dd = 2.2 to 3.3 v 2 i stop f osc = 32.768 mhz v dd = 2.2 to 3.3 v 15 40 (crystal osc mode) a/d in operation v dd = 4.5 to 5.5 v 220 450 a 9 i vr a/d in stop v dd = 4.5 to 5.5 v 2 a 10 resolution 10 bit differential f osc = 1 mhz v dd = vr = 5.0 v 2.5 4.0 linearity error t opr = 25? sequential f osc = 1 mhz v dd = vr = 5.0 v 3.2 5.0 lsb linearity error t opr = 25? f osc = 1 mhz total error v dd = vr = 5.0 v 4.0 6.0 topr = 25? a/d conversion input voltage input current output current supply cerrent dc characteristics ?SM5K3 (t opr = ?0 to +70?, typ. value : v dd = 5.0 or 3.0 v, unless otherwise noted.) parameter symbol conditions min. typ. max. unit note
- 7 - resolution 10 differential f osc = 1.0 mhz v dd = vr = 5.0 v 2.5 4.0 linearity error t opr = 25? sequential f osc = 1 mhz v dd = vr = 5.0 v 3.2 5.0 linearity error t opr = 25? f osc = 1 mhz total error v dd = vr = 5.0 v 4.0 6.0 t opr = 25? v ih1 0.8 x v dd v dd v il1 0 0.2 x v dd v ih2 0.9 x v dd v dd v il2 0 0.1 x v dd v dd = 2.7 to 3.3 v 1.0 25 90 i il1 v in = 0 v v dd = 4.5 to 5.5 v 15 70 250 i ih1 v in = v dd 3.0 i il2 v in = 0 v 1.0 10 i ih2 v in = v dd 1.0 10 v dd = 2.7 to 3.3 v 315 i ol1 v o = 1.0 v v dd = 4.5 to 5.5 v 12 25 v dd = 2.7 to 3.3 v 0.2 1.5 i oh1 v o = v dd ?0.5 v v dd = 4.5 to 5.5 v 0.8 2.2 i ol2 v o = 1.5 v v dd = 4.5 to 5.5 v 4.0 9.0 v dd = 2.7 to 3.3 v 0.2 2.0 i oh2 v o = v dd ?0.5 v v dd = 4.5 to 5.5 v 0.8 2.4 i oh3 v oh = v dd ?1.0 v v dd = 4.5 to 5.5 v 0.5 f osc = 2.0 mhz v dd = 4.5 to 5.5 v 1 200 2 800 i dd v dd = 2.7 to 3.3 v 300 900 f osc = 1.0 mhz v dd = 4.5 to 5.5 v 600 1 400 f osc = 2.0 mhz v dd = 4.5 to 5.5 v 760 1 700 i hlt f osc = 1.0 mhz v dd = 4.5 to 5.5 v 400 1 000 i stop v dd = 2.7 to 5.5 v 5 a/d conversion v dd = 2.7 to 3.3 v 130 350 i vr in operation v dd = 4.5 to 5.5 v 220 500 a/d conversion in stop v dd = 2.7 to 5.5 v 3 ?sm5k4 (t opr = ?0 to +85?, typ. value : v dd = 5.0 or 3.0 v, unless otherwise noted.) SM5K3/sm5k4/sm5k5 parameter symbol conditions min. typ. max. unit note input voltage v 1 v 2 input current ? 3 ? 4 output current ma 5 ma 6 ma 7 supply current ? 8 ? 9 ? 10 a/d conversion reference clock oscillator frequency bit lsb mhz notes : 1. applicable pins : p1 2 , p1 3 , p2 0 -p2 3 , p3 0 -p3 3 (digital input mode), p4 0 -p4 3 , p5 0 -p5 3 * 1 2. applicable pins : osc in , reset, p1 0 , p1 1 3. applicable pins : r eset, p1 0 -p1 3 , p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (digital input mode) * 1 4. applicable pins : p3 0 -p3 3 (analog input mode) 5. applicable pins : p0 0 -p0 3 (high current output) 6. applicable pins : p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (output mode) * 1 7. applicable pins : p3 0 -p3 3 * 2 8. no load (a/d conversion in stop) 9. a/d conversion in operation (a/d conversion enable) 10. a/d conversion in stop (a/d conversion disable) * 1 in case of 32-pin sop and 36-pin qfp. (in case of 30-pin sdip, p5 2 pin dose not exist. in case of 24-pin ssop, p1 2 , p1 3 , p3 3 , p5 0 -p5 3 pins do not exist.) * 2 p3 ports are normally used for input port with pull-up resistor. these ports can be also used as a suspected case of output port. f osc v dd = 4.5 to 5.5 v, rf = 33 k w 1.34 1.67 2.0
SM5K3/sm5k4/sm5k5 - 8 - ?sm5k5 (t opr = ?0 to +70?, typ. value : v dd = 5.0 or 3.0 v, unless otherwise noted.) parameter symbol conditions min. unit note input voltage v ih1 0.8 x v dd 0 0.9 x v dd 0 v dd 0.2 x v dd v dd 0.1 x v dd v v 1 2 input current i il1 v in = 0 v 2 25 25 70 1 1 90 250 2 10 10 ? ? 3 4 output current i ol1 v o = 1.0 v 5 15 0.3 1.0 7 20 300 1 000 15 25 1.5 2.2 35 60 2 000 2 400 ma ? 5 6 supply current i dd f osc = 2 mhz 1 200 300 600 20 40 760 400 15 20 2 10 130 220 2 500 800 1 200 120 160 1 500 900 60 90 2 10 25 300 450 2 ? ? ? ? 7 7 8 9 a/d conversion resolution 10 2.5 3.2 4.0 4.0 5.0 6.0 bit lsb v ih2 v il1 v il2 i il2 i ih1 i ih2 i ol2 i oh1 i oh2 i stop i hlt i vr sequential linearity error differential linearity error total error v dd = vr = 5.0 v v dd = vr = 5.0 v v dd = vr = 5.0 v f osc = 1 mhz t opr = 25? f osc = 1 mhz t opr = 25? f osc = 1 mhz t opr = 25? v in = v dd v in = 0 v v in = v dd v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v o = v dd ?.5 v v o = 0.5 v v o = v dd ?.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 4.5 to 5.5 v a/d in operation ceramic osc mode f osc = 32.768 khz (crystal osc mode) f osc = 1 mhz f osc = 32.768 khz (crystal osc mode) f osc = 1 mhz f osc = 2 mhz f osc = 32.768 khz (crystal osc mode) a/d in stop v dd = 4.5 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 4.5 to 5.5 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 2.2 to 5.5 v v dd = 2.2 to 3.3 v v dd = 4.5 to 5.5 v v dd = 2.2 to 3.3 v v dd = 2.2 to 3.3 v max. typ.
SM5K3/sm5k4/sm5k5 - 9 - notes : 1. applicable pins : p1 2 , p1 3 , p2 0 -p2 3 , p3 0 -p3 3 (digital input mode), p4 0 -p4 3 , p5 0 -p5 3 * 1 2. applicable pins : osc in , reset, p1 0 , p1 1 3. applicable pins : r eset, p1 0 -p1 3 , p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (digital input mode) * 1 4. applicable pins : p3 0 -p3 3 (analog input mode) 5. applicable pins : p0 0 -p0 3 (high current port) 6. applicable pins : p2 0 -p2 3 , p4 0 -p4 3 , p5 0 -p5 3 (output mode) * 1 7. no load (a/d conversion in stop) 8. a/d conversion in operation (operation enable) 9. a/d conversion in stop (operation disable) * 1 in case of 32-pin sop and 36-pin qfp. ( in case of 30-pin sdip, p5 2 dose not exist. in case of 28-pin sop, p5 0 -p5 3 do not exist.) system configuration a register and x register the a register (or accumulator : a cc ) is a 4-bit general purpose register. the register is mainly used in conjunction with the alu, c flag and ram to transfer numerical value and data to perform various operations. the a register is also used to transfer data between input and output pins. the x register (or auxiliary accumulator) is a 4-bit register and can be used as a temporary register. it loads contents of the a register or its content is transferred to the a register. when the table reference instruction pat is used, the x and a registers load rom data. a pair of a and x registers can accommodate 8-bit data. arithmetic and logic unit (alu) and carry signal cy the alu performs 4-bit parallel operation the alu operates binary addition in conjunction with ram, c flag and a register. the carry signal cy is generated if a carry occurs during alu operation. some instructions use cy : adc instruction sets/clears the content of the c flag; adx instruction causes the program to skip the next instruction. note that cy is the symbol for carry signal and not for c flag. 3 3 0 0 a register x register exax instruction fig. 1 data transfer example between a register and x register c areg alu result of operation 4-bit data 4-bit data fig. 2 alu
SM5K3/sm5k4/sm5k5 - 10 - data memory (ram) the data memory (ram) is used to store data up to 4 x 16 x 8 = 512 bits. fig. 3 b register and sb register file (0-7) b m b l 0 1 2 3 4 5 6 7 0123456789abcdef word (0-f h ) 1 word = 4-bit fig. 4 ram file and word b register and sb register ?b register (b m , b l ) the b register is an 8-bit register that is used to specify the ram address. the upper 4-bit section is called b m register and lower 4-bit b l . ?sb register the sb register is an 8-bit register used as the save register for the b register. the contents of b register and sb register can be exchanged through ex instruction. 7 3 0 0 03 ex instruction (swap) sb register b m register b register b l register
SM5K3/sm5k4/sm5k5 - 11 - the program counter pc specifies the rom address. the pc consists of 12-bit as shown in fig. 5 : the upper 6-bit (p u ) represents a page while the lower 6-bit (p l ) denotes a step. the p u section is a register and the p l section, a binary counter. execution of interrupt handling and the table reference instruction pat also automatically uses 1 stage of the stack register sr. program memory (rom) the rom is used to store the program. the capacity of the rom is 2 048-step (32-page by 64- step. see fig. 6). the configuration of the rom and program jumps are illustrated in fig. 7. p u specifies a page (pages 00 h -1f h ) specifies a page (pages 00 h -3f h ) p l program counter pc p u p l push pop sr ( level 1 ) sr ( level 2 ) sr ( level 3 ) sr ( level 4 ) msb lsb stack register sr page step fig. 6 page and step for rom fig. 5 program counter pc and stack register sr program counter pc and stack register sr
SM5K3/sm5k4/sm5k5 - 12 - p u (page) p u (page) start address upon hardware reset front cover of subroutine trs reference to the table during execution of pat instructions interrupt standby released 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h number in a circle is a step number in the program jump. last page, last step (1f3f h ) rtn tlxy rtn trsx trsx tlxy trx rtn callxy trx 2 1 3 2 1 1 1 1 1 2 fig. 7 rom configuration and program jump example
SM5K3/sm5k4/sm5k5 - 13 - output latch register and mode register the SM5K3/5k4/5k5 contain 6 output-latch registers and 8 mode-registers which either latch contents of output ports or control some functions of the SM5K3/5k4/5k5. these registers, their functions and available transfer instructions are shown in table 1 below. an output latch register sets the output level of the pin to which it is connected. refer to the section of ?ode registers concerning about the details mode registers. symbol function out inl out in/tpb anp/orp content of b l p0 output register o o o 0 p1 input register o o 1 p2 i/o register (independent) o o o 2 p3 input register (and analog input) o 3 r3 control register o 3 p4 i/o register o o o 4 p5 i/o register o o o 5 r8 * a/d data/control register o o 8 r9 * a/d data register o o 9 ra * timer/counter register o o a rb * timer/modulo register o o b rc timer control register o o c re interrupt mask register o o e rf p2 directional register o o f table 1 output latch registers and mode registers * 8-bit register note : bit 4 (r84) in the r8 register is read only. (read or write operation of this bit does not affect any other operation.)
SM5K3/sm5k4/sm5k5 - 14 - functional description hardware reset function reset function initializes the SM5K3/5k4/5k5 systems. when the input on the reset pin goes low, the system enters reset condition after 2 command cycles. after the reset pin goes high level, the reset condition is removed as the input pulse from osc in pin repeats 2 15 times, forcing the program counter to start at 0 page and 0 address. initialized status of the system immediately after resetting is shown below. reset causes the following changes. 1) i/o pins are set input. 2) all mode registers are reset. 3) output latch register p0 is reset, causing p0 0 to p0 3 pins go high level. 4) interrupt request flags (ifa, ifb, and ift), interrupt master enable flag (ime) are reset, disabling all interrupts. standby feature the standby function saves power by stopping the program whenever it is not necessary to run. the mode in which the microcomputer is executing the program is called the run mode and the mode in which it stops the program is called the standby mode. standby mode is further divided into two modes : stop mode and halt mode, one of which is selected by halt instruction or stop instruction. upon removal of standby condition, the SM5K3/5k4/5k5 return from the standby mode to the normal run mode. to enter the standby mode, select either stop mode or halt mode whichever is appropriate (fig. 8). table 2 status of flags and registers immediately after reset flag register status flag register status pc 0 ifa flag 0 sp level 1 ifb flag 0 ram undefined ift flag 0 register a undefined ime flag 0 register x undefined c flag undefined p0, p2, p4, p5 output latch register 0 b m , b l registers, sb register undefined timers (ra, rb), divider 0 r3, r8 * , r9, rc, re, rf 0 * the content of the bit r84 is undefined because it is read only.
SM5K3/sm5k4/sm5k5 - 15 - ?blocks stopped during standby mode in the halt mode the system clock generating circuit stops during the halt mode, deactivating all the blocks driven by the system clock. the main clock and dividers remain active. this means that timers can be used while in the halt mode. both internal and external clocks can be used as the count clock. in the stop mode the main clock and system clock stop upon entering the stop mode. therefore, only timers using the external clock remain active. ?counters that the system retains during standby mode the contents that will be retained in the halt mode will also be retained in the stop mode. these items are shown in table 3. operation mode standby mode halt mode run halt command halt mode release event normal operation run stop command stop mode release event stop mode fig. 8 operation shift of program table 3 system contents secured during standby mode flag register output latch register/mode register other ifa flag ifb flag ift flag ime flag c flag a register x register b m , b l register sp sr p0, p2, r3, p5 r8, r9, ra, rb rc, re, rf ram ?releasing events of standby mode (6-type) releasing event flag int/ext maskable / nonmaskable priority reset input external nonmaskable low level input on p1 0 pin ifa external maskable 1 low level input on p1 1 pin ifb external maskable 2 low level input on p1 2 pin external nonmaskable low level input on p1 3 pin external nonmaskable timer overflow ift internal maskable 3
SM5K3/sm5k4/sm5k5 - 16 - ?interrupt used with SM5K3/5k4/5k5 interrupt event occurs on the falling edge of p1 0 or p1 1 pin input, or the overflow at the timer. these events set flags ifa, ifb and ift respectively, that then serve as interrupt request flag. table 4 shows interrupt handling priority level and jump address. table 4 interrupt event summary interrupt event (request flag) jump address priority order interrupt mask flag falling edge of input on p1 0 (ifa) 2 1 re0 falling edge of input on p1 1 (ifb) 2 2 re1 timer overflow (ift) 2 3 re2 page step 0 2 4 ?usage of halt mode and stop mode the system returns back to the normal operation mode upon occurring of a standby mode releasing condition. the halt mode should be used when the system must enter and exit normal operation frequently as in the case of key operation. the halt mode should also be used to keep timers that are operating from the internal clock, while in the standby mode. the stop mode further saves power than the halt mode but requires slightly longer time to return to the normal mode. therefore, the stop mode should be used when the system will not be required to return to the normal mode in a short time. interrupt feature the interrupt block consists of mask flags (bits re0, re1 and re2), ime flag and interrupt request handling circuit. fig. 9 shows the configuration of the interrupt block. mask flag (mode register re) re2 i fa i fb i ft re1 re0 interrupt request flag ime interrupt enable flag (master enable flag) interrupt handling circuit int signal stack register sr program counter pc fig. 9 interrupt block diagram
SM5K3/sm5k4/sm5k5 - 17 - ?ime flag (master enable flag) the ime enables or disables all interrupts at the same time. the ie command, when executed, sets the ime flag and enables the interrupt specified by the mask flag setting. the id command resets the ime flag, disabling process of any interrupt request. setting the ime flag to reset after releasing hardware reset, all interrupts are inhibited. ?mode register re (interrupt mask flag) the mode register re (re0, re1 and re2; interrupt mask flag) individually enables or disables three type of interrupts. timer/counter the SM5K3/5k4/5k5 have a pair of built-in timer/counter. the timer/counter are used to handle periodic interrupts and to count. the overflowing timer can be used to disable the halt mode. the timer/counter serve as interval timer. the timer/counter consists of an 8-bit count register ra, modulo register rb (for counter initial value setting), 15-bit divider and 4-bit mode register rc (for count clock selection). the configuration of the timer/counter is shown in fig. 10. f sys system clock p1 1 pin ( external event clock ) divider mode register ( rc register ) f sys / 2 0 0 3 3 03 0303 47 47 03 15 f sys / 2 7 ax ax i ft modulo register ( rb register ) count register ( ra register ) after setting b l = 0b h out command ( rb ? [ x, a ] ) in command ( [ x, a ] ? rb ) after setting b l = 0a h out command after setting b l = 0a h in command interrupt request flag count clock selsctor fig. 10 configuration of timer/counter ?selecting count clock a count clock is selected by the bit settings in the mode register rc. lower 2-bit of rc bits selected count clock 0 f sys (system clock) 0 f sys /2 7 1 f sys /2 15 1 external event clock (p1 1 ) 1 0 0 1 0 1 table 5 count clock selection
SM5K3/sm5k4/sm5k5 - 18 - a/d conversion mode in the a/d conversion mode, the converter converts the analog input voltage to the digital value. the analog input voltage is successively compared with the internal voltage charged on the weighted capacitor array until its digital equivalent is determined. the resultant digital data is stored into the mode registers r8 and r9. the conversion requires 152.5 s (main clock at 400 khz/system clock at 5 s) or 1.86 ms (main clock at 32.768 khz/system clock at 61 s). comparison mode in the comparison mode, the analog voltage from one of p3 0 to p3 3 pins is compared, in amplitude, with internally generated voltage whose value is set by the mode registers r8 and r9. the result data of the comparison is saved into the bit 4 (bit r84) position of the mode register r8. the comparison cycle lasts 62.5 s (main clock at 400 khz, system clock at 5 s) or 763 s (main clock at 32.768 khz/system clock at 61 s). a/d conversion the SM5K3/5k4/5k5 are provided with a built-in 10-bit a/d converter having 4-channel multiplexer analog inputs. the a/d converter operates in a/d conversion mode and comparison mode. in the a/d conversion mode, the converter converts the analog input from the p3 pin to the digital value; and in the comparison mode, it compares the input analog amplitude with that of a reference voltage set inside the SM5K3/5k4/5k5. the p3 0 to p3 3 pins can be used as analog voltage inputs. one or more of these 4 inputs can be set to assume a/d pin by the bit operation of the mode register r3. one of these a/d pins is further set as analog input by the bit operation of the mode register r8. the a/d converter is controlled by the bits set in the mode register r8. for details of the mode register r8, refer to " mode registers r8 ". configuration of the a/d converter is illustrated in fig. 11. cautions keep the a/d converter reference voltage on the vr pin equal to or below v dd . do not apply the voltage to the vr pin before v dd is applied. ?connect agnd to gnd. fig. 11 a/d converter block diagram p3 0 p3 1 p3 2 p3 3 a/d pins multiplexer normal input pin changeover r3 register a register x, a registers x, a registers a/d control, data (mode register r8 ) a/d data ( mode register r9 ) vr agnd 10-bit d/a comparator control circuit
SM5K3/sm5k4/sm5k5 - 19 - mode registers the registers which control functions of the SM5K3/5k4/5k5 and which serve as counter/timer are commonly referred to as ?ode registers? in the SM5K3/5k4/5k5, r8 to rb are 8-bit mode registers; and r3, rc, re and rf are 4-bit mode registers. to set data into the mode registers, the out command is used; and to check the contents of the mode registers in command is used. r3 (a/d pin selection register) any pin on 4-pin port p3 can be set accommodate analog voltage (hereafter called a/d pin). bit 3 0 bit i (i = 3 to 0) sets p3i pin to either general purpose input or a/d pin 0 | (general purpose) input 1 | a/d input r8 (a/d conversion control & a/d data register) an 8-bit register used to control a/d conversion and storing part of a/d conversion result. it also stores the results of comparison. bit 7 0 bits 7 to 6 storage of a/d conversion result (a/d conversion mode) and setting of internal voltage (comparison mode) use as part of a 10-bit data ragister in combination with mode register r9. ?bit r86 is the lsb. store lower 2-bit of converted data in a/d conversion mode. use as lower 2-bit of internal voltage setting data in comparison mode. bit 5 * a/d operation enable/disable flag 0 | disable (a/d power source off) 1 | enable (a/d power source on) bit 4 storages of comparison result (read only) 0 | p3i pin voltage < internal setting voltage 1 | p3i pin voltage > internal setting voltage (i = 3 to 0) bit 3 * s/r flag (start/clear) 0 | end of operation (or stop) 1 | start of operation (or in operation) bit 2 operation mode selection 0 | a/d conversion 1 | comparison bits 1 to 0 select one of a/d pins as a/d conversion 00 | p3 0 01 | p3 1 10 | p3 2 11 | p3 3 r9 (a/d data register) the register to store the upper 8-bit of 10-bit data resulting from a/d conversion. bit 7 0 bit i (i = 7 to 0) storages of a/d conversion result (a/d conversion mode) and setting of internal voltage (comparison mode) uses as part of a 10-bit data register in combination with mode register r8. ?bit r97 is the msb. ?stores upper 8-bit of a/d conversion result. uses as upper 8-bit of internal voltage setting data in comparison mode. * when operation is end, these bits are cleared. * select one pin which is to be selected by mode register r8.
SM5K3/sm5k4/sm5k5 - 20 - ra (count register) bit 7 0 bit i (i = 7 to 0) count clock input register uses as counter part of timer/counter (count clock input). loads the content of rb to ra when the ra overflows or when out command (b l = 0a h ) is executed. ra ? rb loads the content of ra to x and a registers upon execution of in command (b l = 0a h ). (x, a) ? ra ?bit 7 = msb, bit 0 = lsb rb (modulo register) bit 7 0 bit i (i = 7 to 0) count initial value storage register ?uses as modulo register of timer/counter ?loads the content of rb to x and a registers upon execution of in command (b l = 0b h ) : x = upper bits, a = lower bits. (x, a) ? rb ?loads the contents of x and a registers to rb upon execution of out command (b l = 0b h ) : x = upper bits, a = lower bits. rb ? (x, a) ?bit 7 : msb, bit 0 : lsb rc (timer control) bit 3 0 bit 3 starts up count of the timer. 0 | stop 1 | start bit 2 (unused) bits 1 to 0 select the source clock to the timer. 00 | f sys (system clock) 01 | f sys /2 7 10 | f sys /2 15 11 | falling edge input on p1 1 pin re (interrupt mask flag) bit 3 0 bit 3 (unused) bit 2 removes overflow interrupt from timer or standby condition. 0 | disable 1 | enable bit 1 interrupts on the falling edge of input from p1 1 pin, or releases of standby mode by the low input from p1 1 pin. 0 | disable 1 | enable bit 0 interrupts on the falling edge of input on p1 0 pin, or releases of standby mode by the low input from p1 0 pin. 0 | disable 1 | enable rf (p2 port direction register) bit 3 0 bit i (i = 3 to 0) selection of input pin/output pin 0 | set p2i pin to input. 1 | set p2i pin to output.
SM5K3/sm5k4/sm5k5 - 21 - i/o ports the SM5K3/5k4/5k5 have 24 ports : 8-input, 4- output and 12-i/o port. to verify the input, use suitable instruction to transfer the input on the pin directly to the a register. to select the output latch register to which the content of the a register is to be transferred, and to select the input port from which the signal or data is to be transferred to the a register, use the b l register. for details of b l settings and associated ports, refer to table 1. ?port p0 0 to p0 3 (cmos inverting output port) the data transfers in 4-bit string (use out or outl instruction) or in unit of 1-bit (use anp or orp instruction). ?port p1 0 to p1 3 (input port with pull-up resistor) the data transfers in unit of 4-bit. this port can be used as standby/external interrupt input or count pulse input. the p1 port can also be used as a standby release port without requiring specific setting on p1 2 and p1 3 pins. pins p1 0 and p1 1 require settings through the mode resister re. when using the p1 port as an external interrupt input, use pins p1 0 and p1 1 with suitable settings in the mode register re. when using the p1 port as the count pulse input, use p1 1 pin. ? port p2 0 to p2 3 (i/o port with pull-up resistor ) each bit can be independently be set its direction and can be transferred independently or in combination of other 3-bit. the direction of the bits is determined by the rf register. after reset, the p2 port is set input. ?port p3 0 to p3 3 (input port with pull-up resistor) the data transfers in unit of 4-bit. the port can also be used as a/d analog voltage input. to use the p3 port as the a/d port, set the mode register r3. ?port p4 0 to p4 3 (i/o port with pull-up resistor ) the data transfers in unit of 4-bit. when set output, content of each bit can be set. executing the input instruction (in) sets the p4 ports (p4 0 to p4 3 ) to input; and executing output instruction (out, anp or orp) sets the port to output. after reset, the p4 port is set input. ?port p5 0 to p5 3 (i/o port with pull-up resistor ) the data transfers in unit of 4-bit. when set output, content of each bit can be set. executing the input instruction (in) sets the p5 ports (p5 0 to p5 3 ) to input; and executing output instruction (out, anp or orp) sets the port to output. after reset, the p5 port is set input. flags the SM5K3/5k4/5k5 have 4 flags (c flag and interrupt request flags [ifa, ifb, ift] ), which are used to perform setting and judgments.
SM5K3/sm5k4/sm5k5 - 22 - ?divider the divider consists of 15 divided-by-two dividers, providing 2 (f sys /2 7 , f sys /2 15 ) of 4 count clocks that are fed to the counter ra from the system clock. its configuration is shown below. the divider can be cleared by using the dr instruction. ?oscillator mask option selection of type of oscillator, ceramic or crystal, is made by mask option. system clock (f sys ) main clock (f osc ) osc in osc out cg ( system clock ) 111111111111111 222222222222222 divider (can be cleared by dr instruction) system clock generator (divided-by-two main clock) f sys f sys /2 7 f sys /2 15 fig. 12 main clock and system clock fig. 13 system clock generator and divider system clock generator and dividers ? system clock generator the system clock is the divided-by-two main clock applied through osc in and osc out (see fig. 12). the system clock generator is shown in fig. 13. one system clock cycle period is equal to one instruction execution time when the instruction consists of 1 word. when the ceramic oscillator runs at 400 khz, the system clock fsys is 200 khz. this means that the instruction execution time is 5 s/word. using a 32.768 khz crystal oscillator generates 16.384 khz fsys and the instruction execution time is 61 s/word. the system clock can be used as count input pulse to the timer.
- 23 - instruction set definition of symbols m : content of ram at the address defined by the b register. ? : transfer direction : logical or ? : logical and ? : exclusive or ai : an i bit of a register (i = 3 to 0) push : saves the contents of pc to stack register sr. pop : returns the contents saved in the stack register back to pc. pj : indicates output latch register or input register. pj ( j = 0, 1, 2, 3, 4, 5) rj : mode register. rj register ( j = 3, a, b, c, e, f) rom ( ) : content stored in rom location defined by the value in ( ). cy : carry in alu (independent of c flag) the cy(carry) is a signal which is generated when the alu has been carried by the execution of a command. it is different from the c flag. x : used to represent a group of bits in the content of a register or memory. for example, the x in the ldax instruction denotes the lower 2 digits (i 1 and i 0 ) of a register. ?a bit in a register is affixed to the register symbol, e.g. a bit (i = 0, 1, 2, 3....) of x register is expressed as xi and p (r) register as p (r) i. increment means binary addition of 1 h and decrement addition of f h . skipping an instruction means to ignore that instruction and to do nothing until starting the next instruction. in this sense, an instruction to be skipped is treated as an nop instruction. skipping 1-byte instruction requires 1-cycle, and 2-byte instruction 2-cycle. skipping 1-byte 2-cycle instruction requires 1-cycle. SM5K3/sm5k4/sm5k5 mnemonic machine code operation rom addressing instructions tr x 80 to bf p l ? x (i 5 -i 0 ) tl xy e0 to e7, 00 to ff p u ? x (i 11 -i 6 ) p l ? y (i 5 -i 0 ) trs x c0 to df push, p u ? 01 h , p l ? x (i 4 , i 3 , i 2 , i 1 , i 0 ) call xy f0 to f7 00 to ff push, p u ? x (i 11 -i 6 ) p l ? y (i 5 -i 0 ) rtn 7d pop rtns 7e pop, skip the next step rtni 7f pop, ime ? 1 data load instructions lax x 10 to 1f a ? x (i 3 -i 0 ) lbmx x 30 to 3f b m ? x (i 3 -i 0 ) lblx x 20 to 2f b l ? x (i 3 -i 0 ) lda x 50 to 53 a ? m, b m i ? b m i ? x (i 1 , i 0 ), (i = 1, 0) exc x 54 to 57 m ? a, b m i ? b m i ? x (i 1 , i 0 ), (i = 1, 0) exci x 58 to 5b m ? a, b l ? b l +1 b m i ? b m i ? x (i 1 , i 0 ), (i = 1, 0) skip the next step, if result of b l = 0 excd x 5c to 5f m ? a, b l ? b l ? b m i ? b m i ? x (i 1 , i 0 ), (i = 1, 0) skip the next step, if result of b l is = f h exax 64 a ? x-reg atx 65 x-reg ? a exbm 66 b m ? a exbl 67 b l ? a ex 68 b ? sb instruction summary
- 24 - SM5K3/sm5k4/sm5k5 mnemonic adx x add 7a a ? a+m adc 7b a ? a+m+c, c ? cy skip the next step, if cy = 1 coma 79 a ? a incb 78 b l ? b l +1, skip the next step, if result of b l = 0 decb 7c b l ? b l ?, skip the next step, if result of b l = f h test instructions tam 6f skip the next step, if a = m tc 6e skip the next step, if c = 1 tm x 48 to 4b skip the next step, if mi = 1, (i = 3 to 0) tabl 6b skip the next step, if a = b l tpb x 4c to 4f skip the next step, if p (r) i = 1, (i = i 1 , i 0 ) ta 6c skip the next step, if ifa = 1 ifa ? 0 tb 6d skip the next step, if ifb = 1 ifb ? 0 tt 69 02 skip the next step, if ift = 1 ift ? 0 bit operation instructions sm x 44 to 47 mi ? 1 (i = 3 to 0) rm x 40 to 43 mi ? 0 (i = 3 to 0) sc 61 c ? 1 rc 60 c ? 0 ie 63 ime ? 1 (interrupt enable) id 62 ime ? 0 (interrupt disable) a ? a+x (i 3 -i 0 ) skip the next step, if cy = 1 00 to 0f arithmetic instructions operation machine code mnemonic machine code operation i/o instructions inl 70 a ? p1 outl 71 p0 ? a anp 72 pj ? pj ? a ( j = 0, 2, 4, 5) orp 73 pj ? pj a ( j = 0, 2, 4, 5) in 74 a ? pj ( j = 1, 2, 3, 4, 5) x-reg, a ? rj ( j = 8, 9, a, b) a ? rj ( j = c, e, f) out 75 pj ? a ( j = 0, 2, 4, 5) rj ? x-reg, a ( j = 8, 9, b) ra ? rb rj ? a ( j = 3, c, e, f) table search instruction pat 6a push p u ? 04 h , p l ? (x 1 , x 0 , a) x-reg ? rom h , a ? rom l pop divider operation instruction dr 69 03 divider (f 0 -f 15 ) clear special instructions stop 76 standby mode (stop) halt 77 standby mode (halt) nop 00 no operation
SM5K3/sm5k4/sm5k5 - 25 - system configuration example ?charger controller osc out osc in p4 2 SM5K3/5k5 p4 1 p4 0 vr v dd p0 0 p0 1 p0 2 p0 3 reset gnd agnd p3 0 p2 1 p2 0 battery switching circuit to 10-bit a/d converter dc supply source + osc out osc in p4 2 sm5k4 p4 1 p4 0 p0 0 p0 1 p0 2 p0 3 reset p3 0 p2 1 p2 0 battery switching circuit to 10-bit a/d converter dc supply source v dd v dd v dd + vr gnd agnd
SM5K3/sm5k4/sm5k5 - 26 - 0.1 27.2 16 15 1 30 0.25 0.2 0.25 0.46 0.1 typ. 0.51 min. 0.2 0.2 8.6 4.4 3.85 3.25 typ. 10.16 1.778 0 -15 0.2 m 0.25 30 sdip (sdip030-p-0400) 0.2 1.275 0.1 0.1 2.7 (1.4) 0.2 1.27 0.4 32 1 17 16 20.6 (1.4) 11.3 14.1 0.15 (12.5) 0.1 typ. 0.2 0.4 0.05 0.15 0.1 0.15 m 32 sop (sop032-p-0525)
SM5K3/sm5k4/sm5k5 - 27 - 0.8 0.38 27 19 13.5 (1.75) (1.75) 10.0 13.5 10.0 (1.75) (1.75) 19 10 18 36 28 0.15 (11.5) 0.85 1.45 0.1 typ. 0.1 0.2 0.4 0.2 0.4 0.05 0.2 0.2 0.1 0.15 0.15 m package base plane 36 qfp (qfp036-p-1010) 1.27 0.4 0.15 (10.6) 12.0 0.2 8.6 (1.7) (1.7) 0.1 0.1 0.2 2.2 1.025 18.0 14 15 1 28 0.1 typ. 0.05 0.2 0.3 0.15 0.1 0.12 m 28 sop (sop028-p-0450)
SM5K3/sm5k4/sm5k5 - 28 - 1.05 0.1 0.45 6.0 7.8 0.65 0.27 0.15 12 13 1 24 0.2 7.6 0.1 typ. 0.2 0.4 0.1 0.05 (6.6) 0.1 0.15 0.15 0.15 m 24 ssop (ssop024-p-0275)

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